1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a dual input mode liquid crystal display having high resolution and performing dynamic capacitance compensation (“DCC”).
2. Description of the Related Art
Lighter and thinner personal computers or television sets require lighter and thinner display devices. Since flat panel displays such as liquid crystal displays (“LCDs”) satisfy such requirements, the LCDs have been developed and put to practical use in a variety of fields instead of cathode ray tubes (“CRTs”).
LCDs display desired images by applying an electric field to a liquid crystal layer with dielectric anisotropy between two panels and adjusting the strength of the electric field to control the transmittance of incident light onto the panels.
LCDs are used in notebook computers as well as desktop computers. Computer users desire to see moving pictures by using the computers provided with developed multimedia environments. Thus, it is necessary to improve the response speed of the LCDs.
One exemplary technique for improving the response speed of the LCDs is dynamic capacitance compensation (“DCC”). Now, DCC will be described in detail.
The DCC processes RGB data by comparing gray value for a pixel in a previous frame with gray value for a pixel in a current frame and adding a predetermined value larger than the difference between the gray values to the gray value of the previous frame. A typical duration of one frame is 16.7 msec. Since it takes a time for a liquid crystal material in a pixel to respond to an applied voltage, time delay is inevitable until a desired gray is displayed. The DCC minimizes the time delay by applying a voltage larger than the predetermined voltage for a given gray to the pixel.
FIG. 1 shows an exemplary DCC processing unit of a conventional single input mode LCD. The DCC processing unit is in a timing controller of an LCD and is a part of a data processing block.
A single input mode LCD transmits one data for one clock, while a dual input mode LCD transmits two data for one clock. The dual input mode LCD has an advantage of reducing the clock period by half relative to the single input mode LCD. Accordingly, the dual input mode LCD simultaneously transmits both even and odd image data for one clock.
Referring to FIG. 1, the DCC processing unit includes a DCC block 11, a memory controller 12 and frame memories A and B 13 and 14.
The DCC block 11 receives current frame data from an external graphic source and previous frame data from the frame memory B 14 via the memory controller 12. The DCC block 11 compares the current frame data and the previous frame data and outputs DCC converted data selected from a built-in look-up table (“LUT”) based on the result of the comparison. The optimal DCC data for the current frame data and the previous fame data is given in the LUT. The current frame data is stored in the frame memory A 13 under the control of the memory controller 12. As described above, a conventional single input mode LCD performing the DCC requires two frame memories for respectively storing the current frame data and the previous frame data. Typically, LCDs having low resolutions such as VGA or WXGA grade resolution are single input mode LCDs, while LCDs having high resolutions equal to or more than SXGA grade resolution, which has the greater number of data lines and thus requires high clock frequency for data processing, are dual input mode LCDs.
FIG. 2 shows an exemplary DCC processing unit of a conventional dual input mode LCD. The DCC processing unit is in a timing controller of the LCD.
A DCC processing unit shown in FIG. 2 includes two sub-DCC processing units each processing even data or odd data and having substantially the same configuration as the DCC processing unit shown in FIG. 1. A first sub-DCC processing unit includes a DCC block 21, a memory controller 22, a frame memory C 23 and a frame memory D 24, and processes even data of a current frame. A second sub-DCC processing unit includes a DCC block 31, a memory controller 32, a frame memory A 33 and a frame B 34 and processes odd data of the current frame.
As shown in FIG. 2, the dual input mode LCD employing the DCC requires four frame memories 23, 24, 33, and 34 and thus has a problem of the increased number of frame memories. To solve the problem of the increased number of frame memories, it is suggested that the high resolution LCD employs the single input mode while its timing controller increases the data processing clock frequency. However, the high data processing clock frequency causes electromagnetic interference (“EMI”), which enforces to introduce a filter between the timing controller and the frame memory. This increases the area of a printed circuit board for mounting the timing controller thereon as well as a product cost.